1. Field of the Invention
The present invention relates to an arithmetic operation circuit for conducting multiplication and accumulation.
2. Description of the Related Art
An accumulation circuit has been employed for, a, multiplication and accumulation process, for example, between pixel blocks in an image signal processor, or in an orthogonal transformation, such as DCT (Discrete Cosine Transformation). In the image signal processing example, there is required an accumulated sum operation for matching a block having n.times.n (n=4, 8, . . . ) pixels with a predetermined reference block for motion compensation. Or in the DCT processing example, there is required a multiplication and accumulation process with an n.times.n pixel block and a predetermined coefficient.
A prior art operation circuit for executing an accumulation operation is shown in FIG. 1. In this figure, a multiplicand (an image data) D and a constant C are stored in register 1 and register 2 respectively. C and D are multiplied by a multiplier 3 in the next clock cycle so that a multiplied product C.times.D is stored in a register 4. Next, the value C.times.D of this register 4 is added to an accumulated sum (C D) stored in an accumulator (register) 61 by an adder 5, then the summed result .SIGMA.(C.multidot.D) is stored again in the accumulator 61. Namely, the following operation is carried out. ##EQU1##
This operation is carried out during each clock cycle for each of the pixels of the pixel block consisting of n.times.n pixels, so that the accumulated sum described below, is finally obtained. ##EQU2##
This accumulated sum is further input to a shifter 8 and data having a predetermined word length is shifted therein a predetermined number of times based on a predetermined bit number preset in a shift number setting register 9. The data is output to a round-off circuit 11 in which it is (typically, rounded off by adding 1 to the 1/2 LSB (least significant bit)). The 1/2 least significant bit is the bit adjacent to and less significant than the least significant bit. Thereafter, the result thereof is stored in a register 10. Operation timings of this prior art circuit are shown in the timing charts in FIG. 2. In this figure, the notation "X" indicates data which is not particularly specified. The notation .phi. indicates zero. Cycle number "m" is equal to n.sup.2 in this case. As should be understood from this figure, the accumulated sum of a certain pixel block stored in the accumulated 61 must be cleared in accordance with a CLEAR signal CLRC before processing the next pixel block. A single clock cycle for clearing the contents of the accumulator 61 is required in addition to the cycles for the accumulation process. Therefore, continuity of the accumulation operation is lost. The extra time required for that one cycle lowers the operation speed. Moreover, a circuit is required for interrupting the image signal input to the operation circuit during the clear cycle.
Also, for rounding off the accumulating operation result, the round-off circuit 11 must be provided as an independently additional hardware. Round-off circuit 11, which usually includes an adder circuit, causes a problem in that the circuit configuration becomes large.